1. Field of Invention
The present invention relates generally to a signal processing circuit and a signal processing method applied advantageously to a repeater of a serial digital transmission system. More particularly, the invention relates to a signal processing circuit and a signal processing method, in which input serial digital data obtained by subjecting given digital data to a scrambling process represented by a generating polynomial is descrambled and then scrambled again through a scrambling process based on the same generating polynomial in order to provide output serial digital data, thus implementing an inexpensive and highly-reliable serial transmission system on a small circuit scale, which prevents multi-stage propagation of a pathological signal and minimizes a cumulative increase of jitters during multi-stage repeating sessions.
2. Description of Related Art
Under the SDI (Serial Digital Interface) transmission scheme (standardized by SMPTE-295M) currently in effect for broadcasting equipment, serial digital data is subjected to a scrambling process represented by a generating polynomial of (X.sup.9 +X.sup.4 +1) so as to limit continuations of "0's" or "1's" in the serialized digital data. In order to utilize a coaxial cable that is an unbalanced transmission line, output data is prepared by a neutralizing process effecting conversion from NRZ code to NRZI code. The output data thus acquired is sent on the coaxial cable transmission line.
Under the SDI transmission scheme, as illustratively shown in FIG. 1A, the parallel digital data PDt has a pattern in which 10-bit data of "300" and "198" in hexadecimal occur in turn. In that case, after the scrambling process and/or the NRZ/NRZI conversion are executed, the transmission data TSD may take on a pattern wherein DC components are maximized as shown in FIG. 1B or 1C (called sag data).
When the transmission data TSD is output by the cable driver onto the coaxial cable, the DC components are eliminated. As a result, the waveform of the sag data (in FIG. 1C) sent on the coaxial cable 250 has the positive side level raised and the negative side level lowered as shown in FIG. 2. The data with such a waveform can likely trigger an equalization error in the cable equalizer in any of the repeaters.
Further, the parallel digital data PDt may have a pattern in which 10-bit data patterns of "110" and "200" in hexadecimal occur in turn as illustratively shown in FIG. 3A. In that case, after the scrambling process and/or the NRZ/NRZI conversion are executed, the transmission data TSD may take on a pattern wherein continuations of "0's" and "1's" for 20 clock cycles occur in turn as illustratively shown in FIG. 3B (called bit slip data). When the transmission data TSD has such a bit slip data pattern, the PLL circuit in any of the repeaters receives less phase information for clock regeneration than before, whereby a clock regeneration error is likely to be triggered.
As with the SDI transmission system, there is a case where the repeaters are furnished at intervals on the coaxial cable for multi-stage repeating between the transmitting and the receiving sides. In such a case, the volume of jitters (i.e., amount of temporal fluctuations) in the data being transmitted increases generally in proportion to the repeating stage count raised to the power 1/2. If the transmission data TSD turns into sag data or bit slip data (called a pathological signal hereunder), multi-stage propagation of such a pathological signal can cause the repeaters to accumulate jitters due to the above-described equalization errors and clock regeneration errors. With the transmission data TSD having a pathological signal, the data arriving at the receiving side contains a large volume of jitters. This causes errors in the reception data with growing frequency.
One conventional way of preventing the cumulative increase of jitters generated in the repeaters above is a use of a repeater 270 whose structure is shown in FIG. 4.
The repeater 270 has a decoding part 280 and an encoding part 290 connected in series. Data Din sent on the coaxial cable is input to a cable equalizer 281 in the decoding part 280 for attenuation characteristic compensation. The cable equalizer 281 transmits the data to both a D-type flip-flop 283 and a PLL circuit 282. The PLL circuit 282 generates a serial clock signal SCKr in synchronism with the output data from the cable equalizer 281. The PLL circuit 282 transmits the serial clock signal SCKr to the D-type flip-flop 283. The D-type flip-flop 283 acquires reception data RSD by latching the output data from the cable equalizer 281 using the clock signal SCKr.
An NRZI/NRZ converter 284 receives the reception data RSD and converts it from NRZI code to NRZ code. A descrambler 285 receives and descrambles the converted data and yields serial digital data SDr. The descrambler 285 transmits the serial digital data SDr to an S/P converter 286 (Serial-to-parallel converter). The S/P converter 286 converts the serial digital data SDr into 10-bit parallel digital data PDr in the SDI format. The parallel digital data PDr constitute the output data of the decoding part 280.
The parallel digital data PDr output from the decoding part 280 is fed to a P/S converter 291 (parallel-to-serial converter) in the encoding part 290 for the conversion into serial digital data SDt. A scrambler 292 receives and scrambles the serial digital data SDt. An NRZ/NRZI converter 293 receives the scrambled data and converts it from NRZ code to NRZI code to provide transmission data TSD. A cable driver 294 receives and outputs transmission data TSD as retransmission data Dout onto the coaxial cable.
In the repeater 270 of FIG. 4, the decoding part 280 initially decodes the input data into the parallel digital data PDr. The parallel digital data PDr is input to the encoding part 290 that carries out P/S conversion, scrambling and NRZ/NRZI conversion on the data based on the parallel clock signal PCK from a crystal oscillator 296. This provides the retransmission data Dout free of jitters that existed in the preceding stages.
However, the repeater 270 has the decoding part 280 and the encoding part 290, each of which is constituted by a considerably large circuit. Therefore, when such the repeater 270 is used in each of the repeating stages this considerably causes an increase of the circuit scale of the SDI transmission system and makes the system expensive.